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preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 4096 mb ddr3 C sdram ecc u dimm 240 pin unbuffered ecc u dimm sgu0 4 g 72f 1 b b 1 s a - xx r t 4 gbyte in fbga techn ology rohs compliant *) the refresh rate has to be doubled when 85c preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 this swissbit module is an industry s tandard 240 - pin 8 - byte ddr3 sdram dual - in - line memory module ( u dimm) which is organized as x 72 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr3 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed s equence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr3 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_15 compatible. the ddr3 sdram module uses the serial presence detect (spd) function implemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organiza tion and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank addr. col. addr. refresh module bank select 512 m x 72 bit 9 x 512 m x 8bit ( 4g bit) 1 6 ba0, ba1, ba2 10 8k s0# module dimensions in mm 133.35 (long) x 30(high) x 2.70 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency sgu0 4 g 72f 1 b b 1 sa - bb rt 4g b yte 8.5 gb/s 1.87ns/1066mt/s 7 - 7 - 7 sgu04g72 f1bb1sa - ccrt 4gbyte 10.6 gb/s 1.5ns/1333mt/s 9 - 9 - 9 sgu04g72f1bb1sa - dcrt 4gbyte 12.8 gb/s 1.25ns/1600mt/s 11 - 11 - 11 pin name a0 C a9 , a11 , a13 C a1 5 address inputs a10/ap address input / autoprecharge bit a12/bc address input / burst chop ba0 C ba2 ba nk address inputs dq0 C dq63 data input / output cb0 C cb7 data check bits input / output dm0 C dm8 input data mask dqs0 C dqs8 data strobe, positive line dqs0# - dqs8# data strobe, negative line (only used when differential data strobe mode is enable d) ras# row address strobe cas# column address strobe we# write enable cke0 clock enable figure 1: mechanical dimensions
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 s0# chip select ck0 clock inputs, positive line ck0# clock inputs, negative line event# temperature event: the event# pin is asserted by the temperature sensor when critical v dd supply voltage (1.5v 0.075v) v ref dq reference voltage: dq, dm (v dd /2) v ref ca reference voltage: control, command, and address (v dd /2) v ss ground v tt termination voltage: used for control, command, and address (v dd /2). v ddspd seria l eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa2 presence detect address inputs odt0 on - die termination nc no connection pin configuration frontside pin symbol pin symbol pin symb ol pin symbol pin symbol 1 v refdq 27 dq18 49 nc 75 v dd 101 v ss 2 v ss 28 dq19 50 cke0 76 nc( s1# ) 102 dqs6# 3 dq0 29 v ss 51 v dd 77 nc( rsvd/odt1 ) 103 dqs6 4 dq1 30 dq24 52 ba2 78 v dd 104 v ss 5 v ss 31 dq25 53 nc( err_out# ) 79 nc( s2# ) 105 dq50 6 dqs0# 32 v ss 54 v dd 80 v ss 106 dq51 7 dqs0 33 dqs3# 55 a11 81 dq32 107 v ss 8 v ss 34 dqs3 56 a7 82 dq33 108 dq56 9 dq2 35 v ss 57 v dd 83 v ss 109 dq57 10 dq3 36 dq26 58 a5 84 dqs4# 110 v ss 11 v ss 37 dq27 59 a4 85 dqs4 111 dqs7# 12 dq8 38 v ss 60 v dd 86 v ss 112 dqs 7 13 dq9 39 cb0 61 a2 87 dq34 113 v ss 14 v ss 40 cb1 62 v dd 88 dq35 114 dq58 15 dqs1# 41 v ss 63 ck1 89 v ss 115 dq59 16 dqs1 42 dqs8# 64 ck1# 90 dq40 116 v ss 17 v ss 43 dqs8 65 v dd 91 dq41 117 sa0 18 dq10 44 v ss 66 v dd 92 v ss 118 scl 19 dq11 45 cb2 67 v refca 93 dqs5# 119 sa2 20 v ss 46 cb3 68 nc( par_in ) 94 dqs5 120 v tt 21 dq16 47 v ss 69 v dd 95 v ss 22 dq17 48 nc 70 a10/ ap 96 dq42 23 v ss 71 ba0 97 dq43 24 dqs2# 72 v dd 98 v ss 25 dqs2 73 we# 99 dq48 26 v ss 74 cas# 100 dq49 signa ls in brackets () may be connected at the dimm socket, but are not used on the dimm
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 backside pin symbol pin symbol pin symbol pin symbol pin symbol 121 v ss 147 dq23 169 nc( cke1 ) 195 odt0 221 dm6/dqs15 122 dq4 148 v ss 170 v dd 196 a13 222 nc( dqs15# ) 1 23 dq5 149 dq28 171 a15 197 v dd 223 v ss 124 v ss 150 dq29 172 a14 198 nc( s3# ) 224 dq54 125 dm0/dqs9 151 v ss 173 v dd 199 v ss 225 dq55 126 nc( dqs9# ) 152 dm3/dqs12 174 a12/ bc # 200 dq36 226 v ss 127 v ss 153 nc( dqs12# ) 175 a9 201 dq37 227 dq60 128 dq6 154 v s s 176 v dd 202 v ss 228 dq61 129 dq7 155 dq30 177 a8 203 dm4/dqs13 229 v ss 130 v ss 156 dq31 178 a6 204 nc( dqs13# ) 230 dm7/dqs16 131 dq12 157 v ss 179 v dd 205 v ss 231 nc( dqs16# ) 132 dq13 158 cb4 180 a3 206 dq38 232 v ss 133 v ss 159 cb5 181 a1 207 dq39 233 dq62 134 dm1/dqs10 160 v ss 182 v dd 208 v ss 234 dq63 135 nc( dqs10# ) 161 dm8/dqs17 183 v dd 209 dq44 235 v ss 136 v ss 162 nc( dqs17# ) 184 ck0 210 dq45 236 v ddspd 137 dq14 163 v ss 185 ck0# 211 v ss 237 sa1 138 dq15 164 cb6 186 v dd 212 dm5/dqs14 238 sda 139 v ss 165 cb7 187 event# 213 nc( dqs14# ) 239 v ss 140 dq20 166 v ss 188 a0 214 v ss 240 v tt 141 dq21 167 nc(test) 189 v dd 215 dq46 142 v ss 168 nc( reset# ) 190 ba1 216 dq47 143 dm2/dqs11 191 v dd 217 v ss 144 nc( dqs11# ) 192 ras# 218 dq52 145 v ss 193 s0# 219 dq53 146 dq22 194 v dd 220 v ss signals in brackets () may be connected at the dimm socket, but are not used on the dimm
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 functional block diagramm 4096 mb ddr3 sdram u dimm, 1 rank and 9 components i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 0 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 1 dqs cs dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 dqs 0 dqs 0 dm 0 dqs 1 dqs 1 dm 1 dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 2 dqs cs dqs 2 dqs 2 dm 2 dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 3 dqs cs dqs 3 dqs 3 dm 3 dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 4 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 5 dqs cs dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dqs 4 dm 4 dqs 5 dqs 5 dm 5 dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 6 dqs cs dqs 6 dqs 6 dm 6 dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 7 dqs cs dqs 7 dqs 7 dm 7 dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 v ddspd spd v dd / v ddq d 0 - d 8 v refdq v refca d 0 - d 8 d 0 - d 8 d 0 - d 8 v ss notes : 1 . dq - to - i / o wiring is shown as recommended but may be changed . 2 . dq / dqs / dqs / odt / dm / cke / s relationship must be maintained as shown . 3 . dq , dm , dqs / dqs resistors : refer to associated topology diagram . 4 . refer to the appropriate clock wiring topology under the dimm wiring details section of the jeded document . 5 . for each dram , a unique zq resistor is connected to gnd . the zq resistor is 240 o 1 %. 6 . refer to associated figure for spd details . i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 8 dqs cs dqs 8 dqs 8 dm 8 cb 0 cb 1 cb 2 cb 3 cb 5 cb 4 cb 6 cb 7 ba 0 - ba 2 ba 0 - ba 2 : sdram d 0 - d 8 a 0 - a 15 a 0 - a 15 : sdram d 0 - d 8 ras ras : sdram d 0 - d 8 cas cas : sdram d 0 - d 8 we we : sdram d 0 - d 8 odt 0 odt : sdram d 0 - d 8 cke 0 cke : sdram d 0 - d 8 ck 0 ck : sdram d 0 - d 8 ck 0 ck : sdram d 0 - d 8 reset reset : sdram d 0 - d 8
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 maximum electrical dc characteristi cs parameter/ condition symbol min max units supply voltage v dd - 0.4 1.975 v i/o supply voltage v dd q - 0.4 1.975 v v dd l supply voltage v dd l - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.425 1.5 1.575 v i/o supply voltage v dd q 1.425 1.5 1.575 v v dd l suppl y voltage v dd l 1.425 1.5 1.575 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.175 - v input low (logic 0) voltage v il (ac) - v ref - 0.175 v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gr oss estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 i dd specifications and conditions (0c t case + 85c, v dd q = +1.5 v 0.075v, v dd = +1.5v 0.075v) parameter & test condition symbol max. unit 12800 cl11 10600 cl9 8500 cl7 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 405 360 360 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 495 450 450 ma precharge power - down current: all device banks idle ; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 135 135 135 ma slow exit 135 135 135 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 180 180 180 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and add ress bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 225 225 180 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dq s are floating at v ref (always fast exit) i dd3p 180 180 180 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus i nputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 270 270 270 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 900 765 630 ma
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 parameter & test condition symbol max. unit 12800 cl11 10600 cl9 8500 cl7 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is hi gh between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 990 810 675 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 1305 1305 1080 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 135 135 135 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1575 1530 1170 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 12800 cl11 10600 cl9 8500 cl7 unit cl (i dd ) 11 9 7 t ck t rcd (i dd ) 13.75 13.5 13.125 ns t rc (i dd ) 48.75 49.5 50.625 ns t rrd (i dd ) 6.25 6 7.5 ns t ck (i dd ) 1.25 1.5 1.87 ns t ras min (i dd ) 35 36 37.5 ns t ras max (i dd ) 70200 70200 70200 ns t rp (i dd ) 13.75 13.5 13.125 ns t rfc (i dd ) 260 260 260 t ck
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical c haracteristics and recommended ac operating conditions (0c t case , + 85c, v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 8500 cl7 parameter symbol min max min max min max unit clock cycle time cl = 11 t ck (11) 1.25 1.5 - - - - ns cl = 10 t ck (10) 1.5 <1.8 75 1.5 <1.875 - - ns cl = 9 t ck (9) 1.5 <1.875 1.5 <1.875 - - ns cl = 8 t ck (8) 1.875 <2.5 1.875 <2.5 1.875 <2.5 ns cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 1.875 <2.5 ns cl = 6 t ck (6) 2.5 3.3 2.5 3.3 2.5 3.3 ns cl = 5 t ck (5) 3.0 3.3 3.0 3.3 3.0 3. 3 ns read cmd to 1 st data t aa 13.75 - 13.5 - 13.125 - ns ck high - level width t ch (avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck ck low - level width t cl (avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz - 225 - 250 - 300 ps data - out low - impedance window from ck/ck# t lz - 450 225 - 500 250 - 600 300 ps dq and dm input pulse width ( for each input ) t dipw 360 - 400 - 490 - ps dq - dqs hold, dqs to first dq to go non - valid, per access t qh 0.38 - 0.38 - 0.38 - t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs read preamble t rpre 0.9 note 1 0.9 note 1 0.9 note 1 t ck dqs read postamble t rpst 0.3 note 2 0.3 note 2 0.3 note 2 t ck dqs write pr eamble t wpre 0.9 - 0.9 - 0.9 - t ck dqs write postamble t wpst 0.3 - 0.3 - 0.3 - t ck 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max) the dq, dqs setup and hold times as well as command/address setup and hold ti mes need to be calculated using the respective component data sheets with derating tables and the driver slew rate in combination with the jedec min/max routing information
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating cond itions (continued) (0c t case + 85c ; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 8500 cl7 parameter symbol min max min max min max unit cas# to cas# command delay t ccd 4 - 4 - 4 - t ck active to active ( same bank) command period t rc 48.75 - 49.5 - 50.625 - ns active bank a to active bank b command t rrd max 4nck,6ns - max 4nck, 6 ns - max 4nck,7.5ns - ns active to read or write delay t rcd 13.75 - 13.5 - 13.125 - ns four bank activate period 1k page size t faw 30 - 30 - 37.5 - ns 2k page size 40 - 45 - 50 - active to precharge command t ras 35 70200 70200 70200 t rtp max 4nck,7.5ns - max 4nck,7.5ns - max 4nck,7.5ns - ns write recovery time t wr 15 - 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck - t wr + t rp /t ck - t wr + t rp /t ck - ns internal write to read command delay t wtr max 4nck,7.5ns - max 4nck,7.5ns - max 4nck,7.5ns - ns precharge command period t rp 13.75 - 13. 5 - 13.125 - ns load mode command cycle time t mrd 4 - 4 - 4 - t ck refresh to active or refresh to refresh command interval t rfc 260 70200 70200 70200 0 c t case 85 c t refi - 7.8 - 7.8 - 7.8 s 85 c < t case 95 c t refi (it) - 3.9 - 3.9 - 3.9 rtt turn - on from odtl on reference t aon - 2 25 2 25 - 250 250 - 300 300 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 0.3 0.7 t ck asynchronous rtt tur n - on delay (power down with dll off) t aonpd 2 8,5 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 t ck first dqs, dqs# rising edge t wlmrd 40 - 40 - 40 - t ck dqs, dqs# delay t wldqsen 25 - 25 - 25 - t ck
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c ; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 8500 cl7 parameter symbol min max min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns - max 5nck, t rf c + 10ns - max 5nck, t rfc + 10ns - t ck begin power supply ramp to power supplies stable t v ddpr - 200 - 200 - 200 ms reset# low to power supplies stable t rps 0 200 - 200 - 200 ms reset# low to i/o and rtt high - z t ioz - 20 - 20 - 20 ns exit precharge pow er - down to any non - read command t xp max 3nck,6ns - max 3nck,6ns - max 3nck,7.5ns - t ck cke minimum high/low time t cke max 3nck, 5 ns - max 3nck, 5.625ns - max 3nck, 5.625ns - t ck temperature sensor with serial presence - detect eeprom temperature sensor with serial presence - detect eeprom operating conditions parameter / condition symbol min max unit supply voltage v ddspd +3 +3.6 v supply current: v dd = 3.3v i dd +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v dds pd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: i out = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range tbd tbd c temperature sensor accuracy tbd tbd c s c l s d a e v e n t s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 a.c. characteristics o f temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c symbol parameter / condition min max unit f scl scl clock frequency 10 400 khz t buf bus free time between stop and start 1300 ns t f sda fall time 300 ns t r sda rise time 300 ns t hd:dat dat a hold time (accepted for input data) 0 ns data hold time (guaranteed for output data) 300 900 ns t h:sta start condition hold time 600 ns t high high period of scl 600 ns t low low period of scl 1300 ns t su:dat data setup time 100 ns t su:sta star t condition setup time 600 ns t su:sto stop condition setup time 600 ns t timeout smbus scl clock low timeout 25 35 ms t i noise pulse filtered at scl and sda inputs 100 ns t wr write cycle time 5 ms t pu power - up delay to valid temperature recording 100 ms temperature characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c parameter test conditions/comments max unit temperature reading error class b, jc42.4 compliant +75c t a +95c, active range +40c t a +12 40c t a +125c, sensing range 1 ja junction - to - ambient (still air) 92 c/w 1 power dissipation is defined as p j = (t j ? t a )/ ja , where tj is the junction temperature and ta is the ambient temperature. the thermal resistance value refers to the case of a package being used on a standard 2 - layer pcb. slave address bits of temperature sensor device device type ide ntifier select address signals r/w# b7 1 b6 b5 b4 b3 b2 b1 b0 eeprom 1 0 1 0 a 2 a 1 a 0 r/w# temp. sensor 0 0 1 1 a 2 a 1 a 0 r/w# 1 the most significant bit, b7, is sent first.
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 serial presence - detect matrix byte byte description 12800 cl11 10600 cl9 850 0 cl7 0 crc range, eeprom bytes, bytes used 0x92 1 spd revison 0x1 1 2 dram device type 0x0b 3 module type (form factor) 0x02 4 sdram device density & banks 0x0 4 5 sdram device row & column count 0x 21 6 byte 6 reserved 0x00 7 module ranks & device d q count 0x01 8 ecc tag & module memory bus width 0x0 b 9 fine timebase dividend/divisor 0x 11 10 medium timebase dividend 0x01 11 medium timebase divisor 0x08 12 min sdram cycle time (t ck min ) 0x0a 0x0c 0x0f 13 byte 13 reserved 0x00 14 cas latencies s upported (cl4 => cl11) 0xfe 0x7e 0x1e 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time (t aa min ) 0x69 17 min write recovery time ( t wr min ) 0x78 18 min ras# to cas# delay (t rcd min ) 0x69 19 min row active to row active delay (t rrd min ) 0x30 0x3c 20 min row precharge delay (t rp min ) 0x69 21 upper nibble for t ras & t rc 0x11 22 min active to precharge delay (t ras min ) 0x18 0x20 0x2c 23 min active to active/refresh delay (t rc min ) 0x81 0x89 0x95 24 min refresh recovery delay ( t rfc min ) lsb 0x 20 25 min refresh recovery delay (t rfc min ) msb 0x0 8 26 min internal write to read cmd delay ( t wtr min ) 0x3c 27 min internal read to precharge cmd delay ( t rtp min ) 0x3c 28 min four active window delay (t faw min ) msb 0x00 0x01 29 min four a ctive window delay (t faw min ) lsb 0xf0 0x2c 30 sdram device output drivers supported 0x8 3 31 sdram device thermal & refresh options 0x0 1 32 ddr3 - module thermal sensor 0x80
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 byte byte description 12800 cl11 10600 cl9 8500 cl7 3 3 - 59 bytes 3 3 - 59 reserv ed 0x00 60 module height (nominal) 0x0f 61 module thickness (max) 0x01 62 reference raw card id 0x0 3 63 address mapping edge conector to dram 0x00 64 - 116 bytes 64 - 116 reseved 0x00 117 module mfr id (lsb) 0x83 118 module mfr id (msb) 0xda 119 module mfr location id 0x01 (swi t zerland) 0x02 (germany) 0x03 (usa) 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0x 6062 0 xb5bc 0x 1614 128 - 145 module part number "sgu0 4 g 72f1 b b 1sa - xx" 146 module die rev x 147 module pcb rev x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0x ce 150 - 175 mfr reserved bytes 150 - 175 0x00 176 - 255 customer reserved bytes 176 - 255 0xff part number code s g u 0 4 g 72 f 1 b b 1 sa - dc * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr3 - 1600 m t/s sdram ddr3 240 pin udimm chip vendor ( samsung ) capacity ( 4 gb yte ) 1 module rank width (72bit) chip rev. b pcb - type ( b63urcd 0.90 ) chip organisation x8 * optional / additional information
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 revision history revision changes date 0.9 preliminary revision 17.04.2013
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 locations swissbit ag industriestrasse 4 ch C 9552 brons chhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _______________________ ______ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________
preliminary data sheet rev.0.9 17.04.2013 swissbit ag industrie strasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 17 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole responsibility t hat the product product type: 4 gb ddr3 ecc udimm brand name: swissmemory? product series: ddr3 udimm part number: sgu0 4 g72f 1 b b 1sa - xxxrt to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive restricti on of the use of certain hazardous substances 2011/65/eu swissbit ag, april 2013 manuela k?gel head of quality management

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